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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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MC68HC68T1 Real-Time Clock plus RAM with Serial Interface
CMOS
The MC68HC68T1 HCMOS Clock/RAM peripheral contains a real-time clock/calendar, a 32 x 8 static RAM, and a synchronous, serial, three-wire interface for communication with a microcontroller or processor. Operating in a burst mode, successive Clock/RAM locations can be read or written using only a single starting address. An on-chip oscillator allows acceptance of a selectable crystal frequency or the device can be programmed to accept a 50/60 Hz line input frequency. The LINE and system voltage (VSYS) pins give the MC68HC68T1 the capability for sensing power-up/power-down conditions, a capability useful for battery-backup systems. The device has an interrupt output capable of signaling a microcontroller or processor of an alarm, periodic interrupt, or power sense condition. An alarm can be set for comparison with the seconds, minutes, and hours registers. This alarm can be used in conjunction with the power supply enable (PSE) output to initiate a system power-up sequence if the VSYS pin is powered to the proper level. A software power-down sequence can be initiated by setting a bit in the interrupt control register. This applies a reset to the CPU via the CPUR pin, sets the clock out (CLKOUT) and PSE pins low, and disables the serial interface. This condition is held until a rising edge is sensed on the VSYS input pin, signaling system power coming on, or by activation of a previously enabled interrupt if the VSYS pin is powered up. A watchdog circuit can be enabled that requires the microcontroller or processor to toggle the slave select (SS) pin of the MC68HC68T1 periodically without performing a serial transfer. If this condition is not met, the CPUR line resets the CPU. * Full Clock Features -- Seconds, Minutes, Hours (AM/PM), Day-of-Week, Date, Month, Year (0 - 99), Auto Leap Year * 32-Byte General Purpose RAM * Direct Interface to Motorola SPI and National MICROWIREt Serial Data Ports * Minimum Timekeeping Voltage: 2.2 V * Burst Mode for Reading/Writing Successive Addresses in Clock/RAM * Selectable Crystal or 50/60 Hz Line Input Frequency * Clock Registers Utilize BCD Data * Buffered Clock Output for Driving CPU Clock, Timer, Colon, or LCD Backplane * Power-On Reset with First Time-Up Bit * Freeze Circuit Eliminates Software Overhead During a Clock Read * Three Independent Interrupt Modes -- Alarm, Periodic, or Power-Down * CPU Reset Output -- Provides Orderly Power-Up/Power-Down * Watchdog Circuit * Pin-for-Pin Replacement for CDP68HC68T1 * Chip Complexity: 8500 FETs or 2125 Equivalent Gates * Also See Application Notes ANE425 "Use of the MC68HC68T1 RTC with M6805 Microprocessor", AN457 "Providing a Real-Time Clock for the MC68302", and AN1065 "Use of the MC68HC68T1 Real-Time Clock with Multiple Time Bases"
MICROWIRE is a trademark of National Semiconductor Inc.
REV 2 2/96
16 1
P SUFFIX PLASTIC DIP CASE 648
16 1
DW SUFFIX SOG PACKAGE CASE 751G
ORDERING INFORMATION
MC68HC68T1P Plastic DIP MC68HC68T1DW SOG Package
PIN ASSIGNMENT
CLKOUT CPUR INT SCK MOSI MISO SS VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD XTALout XTALin VBATT VSYS LINE POR PSE
(c) Motorola, Inc. 1996 MOTOROLA
MC68HC68T1 1
BLOCK DIAGRAM
AM/PM AND HOUR LOGIC CALENDAR LOGIC
XTALin XTALout
14 15 OSCILLATOR PRESCALE SECOND MINUTE HOUR DAY/ DATE MONTH
VBATT LINE
13 11
50/60 Hz STOP/START PRESCALE SELECT CLOCK SELECT
CLKOUT INT
1 3
CLOCK AND INT LOGIC
CLOCK CONTROL REG INTERRUPT CONTROL REG
8-BIT DATA BUS
COMPARATOR SECOND LATCH MINUTE LATCH HOUR LATCH YEAR
VSYS POR PSE CPUR SCK MISO MOSI SS
12 10 9 2 4 6 5 7
POWER SENSE CONTROL
STATUS REGISTER 32 x 8 RAM
SERIAL INTERFACE
FREEZE CIRCUIT
PIN 16 = VDD PIN 8 = VSS
MC68HC68T1 2
MOTOROLA
ABSOLUTE MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Vin Vout Iin Iout IDD PD Tstg TL Parameter DC Supply Voltage DC Input Voltage (except Line Input**) DC Output Voltage DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VDD and VSS Pins Power Dissipation, per Package*** Storage Temperature Lead Temperature (10-Second Soldering) Value - 0.5 to + 7.0 - 0.5 to VDD + 0.5 - 0.5 to VDD + 0.5 10 10 30 500 - 65 to + 150 260 Unit V V V mA mA mA mW C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
* Maximum Ratings are those values beyond which damage to the device may occur. ** See Electrical Characteristics Table. *** Power Dissipation Temperature Derating: 12 mW/_C from 65 to 85_C.
ELECTRICAL CHARACTERISTICS (TA = - 40 to + 85_C, Voltages Referenced to VSS)
Symbol VDD V(stdby) VIL Parameter Power Supply Voltage Range Minimum Standby (Timekeeping) Voltage* Maximum Low-Level Input Voltage Test Condition VDD V -- -- 3.0 4.5 6.0 3.0 4.5 6.0 Power Sense Mode Iout = 0 mA Iout = 1.6 mA Iout = 0 mA Iout = 1.6 mA Vin = VDD or VSS Vin = VSS Vin = VDD Vout = VDD or VSS Vin = VDD or VSS, All Input; Iout = 0 mA fXTALin = 32 kHz Iout = 0 mA, fXTALin = 1 MHz Vin = VDD or VSS, all fXTALin = 2 MHz inputs except XTALin, fXTALin = 4 MHz Clock Out Disabled, No Serial Access Cycles Iout = 0 mA, Vin = VDD or VSS, Clock Out Disabled, No Serial Access Cycles fXTALin = 32 kHz fXTALin = 1 MHz fXTALin = 2 MHz fXTALin = 4 MHz 5.0 4.5 4.5 6.0 6.0 6.0 6.0 6.0 5.0 Guaranteed Limit 3.0 to 6.0 2.2 0.9 1.35 1.8 2.1 3.15 4.2 12 0.1 0.4 4.4 3.7 1 - 1.0 100 10 50 0.1 0.6 0.84 1.2 0.024 0.12 0.24 0.5 Unit V V V
VIH
Minimum High-Level Input Voltage
V
Vin VOL VOH Iin IIL IIH IOZ IDD IDD
Maximum Input Voltage, Line Input Maximum Low-Level Output Voltage Minimum High-Level Output Voltage Maximum Input Current, Except SS Maximum Low-Level Input Current, SS Maximum Pull-Down Current, SS Maximum Three-State Leakage Current Maximum Quiescent Supply Current Maximum RMS Operating Supply Current Crystal Operation
V p-p V V
mA mA mA mA mA
mA
Maximum RMS Operating Supply Current External Frequency Source Driving XTALin, XTALout Open
5.0
Ibatt
Maximum RMS Standby Current Crystal Operation
fXTALin = 32 kHz VBATT = 3.0 V, fXTALin = 1 MHz VSYS = 0.0 V, fXTALin = 2 MHz VDD = 0.0 V, fXTALin = 4 MHz Iout = 0 mA, Vin = Don't Care, all inputs except XTALin, Clock Out Disabled, No Serial Access Cycles
0.0
25 250 360 600
mA
* Timekeeping function only, no read/write accesses. Data in the registers and RAM retained.
MOTOROLA
MC68HC68T1 3
AC ELECTRICAL CHARACTERISTICS (TA = - 40 to + 85_C, CL = 200 pF, Input tr = tf = 6 ns, Voltages Referenced to VSS)
Symbol fSCK Parameter Maximum Clock Frequency (Refer to SCK tw, below) Figure No. 1, 2, 3 VDD V 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 -- Guaranteed Limit -- 2.1 2.1 200 100 100 200 100 100 200 100 100 200 100 100 10 Unit MHz
tPLH, tPHL tPLZ, tPHZ tPZL, tPZH tTLH, tTHL Cin
Maximum Propagation Delay, SCK to MISO
2, 3
ns
Maximum Propagation Delay, SS to MISO
2, 4
ns
Maximum Propagation Delay, SCK to MISO
2, 4
ns
Maximum Output Transition Time, Any Output (Measured Between 70% VDD and 20% VDD) Maximum Input Capacitance
2, 3
ns
pF
TIMING REQUIREMENTS (TA = - 40 to + 85_C, Input tr = tf = 6 ns, Voltages Referenced to VSS)
Symbol tsu Minimum Setup Time, SS to SCK Parameter Figure No. 1, 2 VDD V 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 1, 2 3.0 4.5 6.0 Guaranteed Limit 200 100 100 200 100 100 250 125 125 200 100 100 200 200 200 400 200 200 -- 100 100 -- 2 2 Unit ns
tsu
Minimum Setup Time, MOSI to SCK
1, 2
ns
th
Minimum Hold Time, SCK to SS
1, 2
ns
th
Minimum Hold Time, SCK to MOSI
1, 2
ns
trec
Minimum Recovery Time, SCK
1, 2
ns
tw(H), tw(L) tw
Minimum Pulse Width, SCK
1, 2
ns
Minimum Pulse Width, POR
ns
tr, tf
Maximum Input Rise and Fall Times (Except XTALin and POR) (Measured Between 70% VDD and 20% VDD)
ms
MC68HC68T1 4
MOTOROLA
SS tsu tw(L) SCK tw(H) 1/fSCK MOSI W/R A6 A5 A0 tr trec tf th
-- VDD -- VSS
-- VDD -- VSS
th D7O
tsu D6O D1N D0N -- VDD -- VSS
NOTE: Measurement points are VIL and VIH unless otherwise noted on the AC Electrical Characteristics table.
Figure 1. Write Cycle
SS tsu tw(L) SCK tw(H) 1/fSCK MOSI W/R A6 th tsu A5 A0 tPLH, tPHL tpZL, tpZH MISO D7O D6O tPLZ, tPHZ D1N D0N trec tr
-- VDD -- VSS tf th
-- VDD -- VSS
-- VDD -- VSS
HIGH IMPEDANCE
tTLH, tTHL NOTE: Measurement points are VOL, VOH, VIL, and VIH unless otherwise noted on the AC Electrical Characteristics table.
Figure 2. Read Cycle
TEST POINT DEVICE UNDER TEST OUTPUT CL* DEVICE UNDER TEST
TEST POINT OUTPUT CL*
CONNECT TO VDD WHEN TESTING tPLZ AND tPZL CONNECT TO VSS WHEN TESTING tPHZ AND tPZH
* Includes all probe and fixture capacitance.
* Includes all probe and fixture capacitance.
Figure 3. Test Circuit
Figure 4. Test Circuit
MOTOROLA
MC68HC68T1 5
OPERATING CHARACTERISTICS
The real-time clock consists of a clock/calendar and a 32 x 8 RAM (see Figure 5). Communication with the device may be established via a serial peripheral interface (SPI) or MICROWIRE bus. In addition to the clock/calendar data from seconds to years, and systems flexibility provided by the 32-byte RAM, the clock features computer handshaking with an interrupt output and a separate square-wave clock output that can be one of seven different frequencies. An alarm circuit is available that compares the alarm latches with the seconds, minutes, and hours time counters and activates the interrupt output when they are equal. The clock is specifically designed to aid in power-up/power-down applications and offers several pins to aid the designer of battery-backup systems. CLOCK/CALENDAR The clock/calendar portion of this device consists of a long string of counters that is toggled by a 1 Hz input. The 1 Hz input is derived from the on-chip oscillator that utilizes one of four possible external crystals or that can be driven by an external frequency source. The 1 Hz trigger to the counters can also be supplied by a 50 or 60 Hz source that is connected to the LINE input pin. The time counters offer seconds, minutes, and hours data in 12- or 24-hour format. An AM/PM indicator is available that once set, toggles at 12:00 AM and 12:00 PM. The calendar counters consist of day of week, date of month, month, and year information. Data in the counters is in BCD format. The hours counter utilizes BCD for hours data plus bits for 12/24 hour and AM/PM modes. The seven time counters are read serially at addresses $20 through $26. The time counters are written to at addresses $A0 through $A6. (See Figures 5 and 6 and Table 1.) 32 x 8 GENERAL-PURPOSE RAM The real-time clock also has a static 32 x 8 RAM. The RAM is read at addresses $00 through $1F and written to at addresses $80 through $9F (see Figure 5). ALARM The alarm is set by accessing the three alarm latches and loading the desired data. (See Serial Peripheral Interface.) The alarm latches consist of seconds, minutes, and hours registers. When their outputs equal the values of the seconds, minutes, and hours time counters, an interrupt is generated. The interrupt output goes low if the alarm bit in the status register is set and the interrupt output is activated after an alarm time is sensed (see Pin Descriptions, INT Pin). To preclude a false interrupt when loading the time counters, the alarm interrupt bit in the interrupt control register should be reset. This procedure is not required when the alarm time is being loaded. WATCHDOG FUNCTION When Watchdog (bit 7) in the interrupt control register is set high, the clock's slave select pin must be toggled at regular intervals without a serial data transfer. If SS is not toggled at the rate shown in Table 2, the MC68HC68T1 supplies a
CPU reset pulse at Pin 2 and Watchdog (bit 6) in the status register is set (see Figure 7). Typical service and reset times are shown in Table 2. CLOCK OUT The value in the three least significant bits of the clock control register selects one of seven possible output frequencies. (See Clock Control Register.) This square-wave signal is available at the CLKOUT pin. When the power- down operation is initialized, the output is reset low. CONTROL REGISTER AND STATUS REGISTER The operation of the real-time clock is controlled by the clock control and interrupt control registers, which are read/ write registers. Another register, the status register, is available to indicate the operating conditions. The status register is a read-only register, and a read operation resets status bits. MODE SELECT The voltage level that is present at the VSYS input pin at the end of power-on reset selects the device to be in the single- supply mode or battery-backup mode. Single-Supply Mode If VSYS is powered up when power-on reset is completed; CLKOUT, PSE, and CPUR are enabled high and the device is completely operational. CPUR is asserted low if the voltage level at the VSYS pin subsequently falls below VBATT + 0.7 V. If CLKOUT, PSE, and CPUR are reset low due to a power-down instruction, V SYS brought low and then powered high re-enables these outputs. An example of the single-supply mode is where only one supply is available and VDD, V BATT, and V SYS are tied together to the supply. Battery-Backup Mode If VSYS is not powered up (VSYS = 0 V) at the end of power-on reset, CLKOUT, PSE, CPUR, and SS are disabled (CLKOUT, PSE, and CPUR low). This condition is held until VSYS rises to a threshold (approximately 0.7 V) above V BATT. CLKOUT, PSE, and CPUR are then enabled and the device is operational. If V SYS falls below a threshold above VBATT, the outputs CLKOUT, PSE, and CPUR are reset low. An example of battery-backup operation occurs if V SYS is tied to the 5 V supply and is not receiving voltage from a supply. A rechargeable battery is connected to the V BATT pin, causing a POR while VSYS = 0 V. The device retains data and keeps time down to a minimum VBATT voltage of 2.2 V. The power consumption may not settle to the specified limit until main power is cycled once. POWER CONTROL Power control is composed of two operations, power- sense and power-down/power-up. Two pins are involved in power sensing, the LINE input pin and the INT output pin. Two additional pins, PSE and VSYS, are utilized during power-down/power-up operation.
MC68HC68T1 6
MOTOROLA
FREEZE FUNCTION The freeze function prevents an increment of the time counters, if any of the registers are being read. Also, alarm operation is delayed if the registers are being read. This causes the clock to lose time with increasing rates of acceleration. POWER SENSING When power sensing is enabled (Power Sense Bit in the interrupt control register), ac/dc transitions are sensed at the LINE input pin. Threshold detectors determine when transitions cease. After a delay of 2.68 to 4.64 ms plus the external input RC circuit time constant, an interrupt true bit is set high in the status register. This bit can then be sampled to see if system power has turned back on (see Figure 8). The power-sense circuitry operates by sensing the level of the voltage present at the LINE input pin. This voltage is centered around VDD, and as long as the voltage is either plus or minus a threshold (approximately 0.7 V) from VDD, a power sense failure is not indicated. With an ac signal present, remaining in this VDD window longer than a maximum of 4.64 ms activates the power-sense circuit. The larger the amplitude of the signal, the less likely a power failure would be detected. A 50 or 60 Hz, 10 V p-p sine-wave voltage is an acceptable signal to present at the LINE input pin to set up the power-sense function. When ac power fails, an internal circuit pulls the voltage at the line pin within the detection window. Power-Down Power-down is a processor-directed operation. The power-down bit is set in the interrupt control register to initi-
ate power-down operation. During power-down, the power supply enable (PSE) output, normally high, is driven low. The CLKOUT pin is driven low. The CPUR output, connected to the processor reset input pin, is also driven low. In addition, the serial interface (MOSI and MISO) is disabled (see Figure 9).
Power-Up There are four methods that can initiate the power-up mode. Two of the methods require an interrupt to the microcontroller or processor by programming the interrupt control register. The interrupts can be generated by the alarm circuit by setting the alarm bit and the appropriate alarm registers. Also, an interrupt can be generated by programming the periodic interrupt bits in the interrupt control register. VSYS must be at 5 volts for this operation to occur. The third method is by initiating the power sense circuit with the power sense bit in the interrupt control register set to sense power loss along with the VSYS pin to sense subsequent power-up condition (see Figure 10). (Reference Figure 19 for application circuit for third method.) The fourth method that initiates power-up occurs when the level on the VSYS pin rises 0.7 V above the level of the VBATT pin, after previously falling to the level of VBATT while in the battery-backup mode. An interrupt is not generated when the fourth method is utilized. While in the single-supply mode, power-up is initiated when the VSYS pin loses power and then returns high. There is no interrupt generated when using this method (see Figure 11).
MOTOROLA
MC68HC68T1 7
HEXADECIMAL $00 32 BYTES GENERAL-PURPOSE USER RAM READ ADDRESSES ONLY SECONDS MINUTES T H R U HOURS DAY OF THE WEEK DATE OF THE MONTH MONTH $1F $20 YEAR NOT USED NOT USED NOT USED NOT USED T H R U NOT USED NOT USED NOT USED NOT USED NOT USED STATUS REGISTER CLOCK CONTROL REGISTER $32 $33 T H R U $7F $80 32 BYTES GENERAL-PURPOSE USER RAM WRITE ADDRESSES ONLY $9F $A0 T H R U INTERRUPT CONTROL REGISTER
HEXADECIMAL $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F $30 $31 $32
CLOCK/CALENDAR READ ADDRESSES ONLY
HEXADECIMAL SECONDS MINUTES HOURS DAY OF THE WEEK DATE OF THE MONTH MONTH YEAR NOT USED SECONDS ALARM MINUTES ALARM HOURS ALARM NOT USED $A0 $A1 $A2 $A3 $A4 $A5 $A6 $A7 $A8 $A9 $AA $AB $AC $AD $AE $AF $B0 $B1 $B2
NOT USED
CLOCK/CALENDAR WRITE ADDRESSES ONLY
T H R U
NOT USED NOT USED NOT USED NOT USED NOT USED CLOCK CONTROL REGISTER
$B2
INTERRUPT CONTROL REGISTER
Figure 5. Address Map
MC68HC68T1 8
MOTOROLA
HEX ADDRESS READ $20 WRITE $A0 DB7
READ/WRITE REGISTERS DB0 TENS 0 - 5 UNITS 0 - 9
FUNCTION
SECONDS (00 - 59)
$21
$A1 12 HR 24 X
TENS 0 - 5 PM/AM TENS 0 - 2
UNITS 0 - 9
MINUTES (00 - 59) DB7, 1 = 12 HR, 0 = 24 HR DB5, 1 = PM, 0 = AM HOURS (01 - 12 OR 00 - 23) DAY OF WEEK (01 - 07) SUNDAY = 1
$22
$A2
X
UNITS 0 - 9
$23
$A3
X
X
X
X
UNITS 1 - 7
$24
$A4
TENS 0 - 3
UNITS 0 - 9
DATE OF MONTH (01 - 31)
$25
$A5
TENS 0 - 1
UNITS 0 - 9
MONTH (01 - 12) JAN = 1 YEAR (00 - 99)
$26
$A6
TENS 0 - 9
UNITS 0 - 9
$31
$B1
7
6
5
4
3
2
1
0
CLOCK CONTROL REGISTER
$32
$B2
7
6
5
4
3
2
1
0
INTERRUPT CONTROL REGISTER
WRITE-ONLY REGISTERS
N/A
$A8
TENS 0 - 5
UNITS 0 - 9
SECONDS ALARM (00 - 59)
N/A
$A9
TENS 0 - 5
UNITS 0 - 9
MINUTES ALARM (00 - 59) HOURS ALARM (01 - 21 OR 00 - 23) DB5, 1 = PM, 0 = AM IN 12 HR MODE
N/A
$AA
X
X
PM/AM TENS 0 - 2
UNITS 0 - 9
READ-ONLY REGISTER
$B0
N/A
7
6
5
4
3
2
1
0
STATUS REGISTER
RAM DATA BYTE
$00 T0 $1F
$80 T0 $9F
D7
D6
D5
D4
D3
D2
D1
D0
DATA
NOTE: X = Don't Care for Write X = 0 for Read N/A = Not Applicable
Figure 6. Clock/RAM Registers
MOTOROLA
MC68HC68T1 9
Table 1. Clock/Calendar and Alarm Data Modes
Address Location Read $20 $21 $22 Write $A0 $A1 $A2 Seconds Minutes Hours** (12 Hour Mode) Hours (24 Hour Mode) $23 $24 $25 $26 N/A N/A N/A $A3 $A4 $A5 $A6 $A8 $A9 $AA Day of Week (Sunday = 1) Date of Month Month (Jan = 1) Year Seconds Alarm Minutes Alarm Hours Alarm*** (12 Hour Mode) Hours Alarm (24 Hour Mode) Function Decimal Range 0 - 59 0 - 59 1 - 12 0 - 23 1-7 1 - 31 1 - 12 0 - 99 0 - 59 0 - 59 1 - 12 0 - 23 BCD Data Range 00 - 59 00 - 59 81 - 92 (AM) A1 - B2 (PM) 00 - 23 01 - 07 01 - 31 01 - 12 00 - 99 00 - 59 00 - 59 01 - 12 (AM) 21 - 32 (PM) 00 - 23 BCD Date* Example 21 40 90 10 03 16 06 87 21 40 10 10
N/A = Not Applicable * Example: 10:40:21 AM, Tuesday, June 16, 1987. ** Most significant data bit, D7, is "0" for 24-hour mode and "1" for 12-hour mode. Data bit D5 is "1" for PM and "0" for AM in 12-hour mode. *** Data bit D5 is "1" for PM and "0" for AM in 12-hour mode. Data bits D7 and D6 are Don't Cares.
Table 2. Watchdog Service and Reset Times
50 Hz Min Service Time Reset Time -- 20 ms Max 10 ms 40 ms Min -- 16.7 ms 60 Hz Max 8.3 ms 33.3 ms Min -- 15.6 ms XTAL Max 7.8 ms 31.3 ms
NOTE: Reset does not occur immediately after slave select is toggled. Approximately two clock cycles later, reset initiates.
SERVICE TIME
SERVICE TIME
SS
SCK
CPUR
Figure 7. Watchdog Operation Waveforms
MC68HC68T1 10
MOTOROLA
VDD XTALin
XTALout VDD
INT
IRQ
VDD 0V
LINE MSB REAL-TIME CLOCK MC68HC68T1 1 (STATUS REGISTER) LSB MC68HC05C4 CPU
NOTE: A 60 Hz, 10 V p-p sine-wave voltage is an acceptable signal to present at the LINE input pin.
Figure 8. Power Sensing Functional Diagram
TO SYSTEM POWER CONTROL
PSE MSB 1 INTERRUPT CONTROL REGISTER CLKOUT OSC 1 LSB
VDD
CPUR VSYS VBATT MISO MOSI
RESET
SERIAL INTERFACE REAL-TIME CLOCK MC68HC68T1
MC68HC05C4 CPU
Figure 9. Software Power-Down Functional Diagram
MOTOROLA
MC68HC68T1 11
INT
POWER-UP
INTERNAL INTERRUPT SIGNAL
PSE
ALARM CIRCUIT
CPUR
PERIODIC INTERRUPT SIGNAL
CLKOUT
POWER SENSE CIRCUIT
MISO SERIAL INTERFACE REAL-TIME CLOCK MC68HC68T1 NOTE: The VSYS pin must be powered up. MOSI
Figure 10. Power-Up Functional Diagram (Initiated by Internal Interrupt Signal Generation)
VDD
BACKUP SWITCH
PSE
VBATT
POWER SWITCH/ MODE CONTROL CPUR
CLKOUT
VSYS MISO SERIAL INTERFACE MOSI
VBATT
REAL-TIME CLOCK MC68HC68T1
Figure 11. Power-Up Functional Diagram (Initiated by a Rise in Voltage on the VSYS Pin)
MC68HC68T1 12
MOTOROLA
PIN DESCRIPTIONS
CLKOUT Clock Output (Pin 1) This signal is the buffered clock output which can provide one of the seven selectable frequencies (or this output can be reset low). The contents of the three least significant bit positions in the clock control register determine the output frequency (50% duty cycle, except 2 Hz in the 50 Hz time- base mode). During power-down operation (Power-Down bit in the interrupt control register set high), the CLKOUT pin is reset low. CPUR CPU Reset (Pin 2) This pin provides an N channel, open-drain output and requires an external pullup resistor. This active low output can be used to drive the reset pin of a microprocessor to permit orderly power-up/power-down. The CPUR output is low from 15 to 40 ms when the watchdog function detects a CPU failure (see Table 2). The low level time is determined by the input frequency source selected as the time standard. CPUR is reset low when power-down is initiated. INT Interrupt (Pin 3) This active-low output is driven from a single N channel transistor and must be tied to an external pullup resistor. Interrupt is activated to a low level when any one of the following takes place: 1. Power sense operation is selected (Power Sense Bit in the interrupt control register is set high) and a power failure occurs. 2. A previously set alarm time occurs. The alarm bit in the status register and the interrupt signal are delayed 30.5 ms when 32 kHz or 1 MHz operation is selected, 15.3 ms for 2 MHz operation, and 7.6 ms for 4 MHz operation. 3. A previously selected periodic interrupt signal activates. The status register must be read to reset the interrupt output after the selected periodic interval occurs. This is also true when conditions 1 and 2 activate the interrupt. If power- down has been previously selected, the interrupt also sets the power-up function only if power is supplied to the VSYS pin to the proper threshold level above VBATT. SCK Serial Clock (Pin 4) This serial clock input is used to shift data into and out of the on-chip interface logic. SCK retains its previous state if the line driving it goes into a high-impedance state. In other words, if the source driving SCK goes to the high-impedance state, the previous low or high level is retained by on-chip control circuitry. MOSI Master Out Slave In (Pin 5) The serial data present at this port is latched into the interface logic by SCK if the logic is enabled. Data is shifted in,
either on the rising or falling edges of SCK, with the most significant bit (MSB) first. In Motorola's microcomputers with SPI, the state of the CPOL bit determines which is the active edge of SCK. If SCK is high when SS goes high, the state of the CPOL bit is high. Likewise, if a rising edge of SS occurs while SCK is low (see Figure 13), then the CPOL bit in the microcomputer is low. MOSI retains its previous state if the line driving it goes into high-impedance state. In other words, if the source driving MOSI goes to the high-impedance state, the previous low or high level is retained by on-chip control circuitry. MISO Master In Slave Out (Pin 6) The serial data present at this port is shifted out of the interface logic by SCK if the logic is enabled. Data is shifted out, either on the rising or falling edge of SCK, with the most significant bit (MSB) first. The state of the CPOL bit in the microcomputer determines which is the active edge of SCK (see Figure 13). SS Slave Select (Pin 7) When high, the slave select input activates the interface logic; otherwise the logic is in a reset state and the MISO pin is in the high-impedance state. The watchdog circuit is toggled at this pin. SS has an internal pulldown device. Therefore, if SS is in a low state before going to high impedance, SS can be left in a high-impedance state. That is, if the source driving SS goes to the high-impedance state, the previous low level is retained by on-chip control circuitry. VSS Ground (Pin 8) This pin is connected to ground. PSE Power Supply Enable (Pin 9) The power supply enable output is used to control system power and is enabled high under any one of the following conditions: 1. VSYS rises above the VBATT voltage after VSYS is reset low by a system failure. 2. An interrupt occurs (if the VSYS pin is powered up 0.7 V above VBATT). 3. A power-on reset occurs (if the VSYS pin is powered up 0.7 V above VBATT). PSE is reset low by writing a high into the power-down bit of the interrupt control register. POR Power-On Reset (Pin 10) This active-low Schmitt-trigger input generates an internal power-on reset signal using an external RC network (see Figures 18 through 21). Both control registers and frequency dividers for the oscillator and line inputs are reset. The status register is reset except for the first time-up bit (bit 4), which is set high. At the end of the power-on reset, single-supply or battery-backup mode is selected at this time, determined by the state of VSYS. This pin may be more aptly named first-time-up reset.
MOTOROLA
MC68HC68T1 13
LINE Line Sense (Pin 11) The LINE sense input can be used to drive one of two functions. The first function utilizes the input signal as the frequency source for the timekeeping counters. This function is selected by setting the line/XTAL bit high in the clock control register. The second function enables the LINE input to detect a power failure. Threshold detectors operating above and below VDD sense an ac voltage loss. The Power Sense bit in the interrupt control register must be set high, and crystal or external clock source operation is required. The line/XTAL bit in the clock control register must be low to select crystal operation. When Power Sense is enabled, this pin, left unconnected, floats to VDD. This output has no ESD protection diode tied to VDD which allows this pin's voltage to rise above VDD. Care must be taken in the handling of this device. VSYS System Voltage (Pin 12) This input is connected to system voltage. The level on this pin initiates power-up if it rises 0.7 V above the level at the VBATT input pin after previously falling below 0.7 V below VBATT. When power-up is initiated, the PSE pin returns high and the CLKOUT pin is enabled. The CPUR output pin is also set high. Conversely, if the level of the VSYS pin falls below V BATT + 0.7 V, the PSE, CLKOUT, and CPUR pins are placed low. The voltage level present at this pin at the end of POR determines the device's operating mode. VBATT Battery Voltage (Pin 13) This pin is the only oscillator power source and should be connected to the positive terminal of the battery. The VBATT pin always supplies power to the MC68HC68T1, even when the device is not in the battery-backup mode. To maintain timekeeping, the V BATT pin must be at least 2.2 V. When the level on the V SYS pin falls below V BATT + 0.7 V, V BATT is internally connected to the VDD pin. When the LINE input is used as the frequency source, the unused V BATT and XTAL pins may be tied to V SS. Alternatively, if VBATT is connected to VDD, XTAL in can be tied to either VSS or VDD. This output has no ESD protection diode tied to VDD which allows this pin's voltage to rise above VDD. Care must be taken in the handling of this device. XTALin, XTALout Crystal Input/Output (Pins 14, 15) For crystal operation, these two pins are connected to a 32.768 kHz, 1.048576 MHz, 2.097152 MHz, or 4.194304 MHz crystal. If crystal operation is not desired and Line Sense is used as frequency source, connect XTAL in to V DD or V SS (caution: see V BATT pin description) and leave XTA out open. If an external clock is used, connect the external clock to XTAL in and leave XTAL out open. The external clock must swing from at least 30 to 70% of (V DD - V SS). Preferably, this input should swing from VSS to V DD.
VDD Positive Power Supply (Pin 16) For full functionality, the positive power supply pin may range from 3.0 to 6.0 V with respect to VSS. To maintain timekeeping, the minimum standby voltage is 2.2 V with respect to VSS. For proper operation in battery-backup mode, a diode must be placed in series with VDD. CAUTION Data transfer to/from the MC68HC68T1 must not be attempted if the supply voltage falls below 3.0 V.
REGISTERS
CLOCK CONTROL REGISTER (READ/WRITE) -- READ ADDRESS $31/WRITE ADDRESS $B1
MSB D7 START STOP D6 LINE XTAL D5 D4 XTAL XTAL SELECT SELECT 1 0 D3 50 Hz 60 Hz D2 CLK OUT 2 D1 CLK OUT 1 LSB D0 CLK OUT 0
All bits are reset low by a power-on reset.
Start-Stop A high written into this bit enables the counter stages of clock circuitry. A low holds all bits reset in the divider chain from 32 Hz to 1 Hz. The clock out signal selected by bits D0, D1, and D2 is not affected by the stop function except the 1 and 2 Hz outputs. Line/ XTAL When this bit is high, clock operation uses the 50 or 60 cycle input present at the LINE input pin. When the bit is low, the XTALin pin is the source of the time update. XTAL Select Accommodation of one of four possible crystals are selected by the value in bits D4 and D5. 0 = 4.194304 MHz 1 = 2.097152 MHz 2 = 1.048576 MHz 3 = 32.768 kHz
The MC68HC68T1 has an on-chip 150 kW resistor that is switched in series with the internal inverter when 32 kHz is selected via the clock control register. At power-up, the device sets up for a 4 MHz oscillator and the series resistor is not part of the oscillator circuit. Until this resistor is switched in, oscillations may be unstable with the 32 kHz crystal. (See Figure 12.)
XTALin 5 - 30 pF C1 R2 XTALout C2 10 - 40 pF REAL-TIME CLOCK MC68HC68T1 R1
Figure 12. Recommended Oscillator Circuit (C1, C2 Values Depend Upon the Crystal Frequency)
MC68HC68T1 14
MOTOROLA
Resistor R1 is recommended to be 10 MW for 32 kHz operation. Consult crystal manufacturer for R1 value for other frequencies. Resistor R2 must be used in 32 kHz operation only. Use a 200 to 300 kW range. This stabilizes the oscillator until the control register is set properly and reduces standby current. 50 Hz - 60 Hz 50 Hz may be used as the input frequency at the LINE input when this bit is set high; a low accommodates 60 Hz. The power sense bit in the interrupt control register must be reset low for line frequency operation. Clock Out Three bits specify one of the seven frequencies to be used as the square-wave clock output (CLKOUT). 0 = XTAL 1 = XTAL/2 2 = XTAL/4 3 = XTAL/8 4 = Disable (low output) 5 = 1 Hz 6 = 2 Hz 7 = 50/60 Hz for LINE operation 7 = 64 Hz for XTAL operation
Alarm The output of the alarm comparator is enabled when this bit is set high. When an equal comparison occurs between the seconds, minutes, and hours time counters and alarm latches, the interrupt output is activated. When loading the time counters, this bit should be reset low to avoid a false interrupt. This is not required when loading the alarm latches. See INT pin description for explanation of alarm delay. Periodic Select The value in these four bits (D0, D1, D2, and D3) selects the frequency of the periodic output (see Table 3). Table 3. Periodic Interrupt Output Frequencies (at INT Pin)
D3 - D0 Value (Hex) 0 1 2 3 4 5 6 Periodic Interrupt Output Frequency Disable 2048 Hz 1024 Hz 512 Hz 256 Hz 128 Hz 64 Hz 50 or 60 Hz 7 8 9 A 32 Hz 16 Hz 8 Hz 4 Hz 2 Hz 1 Hz 1 Cycle per Minute 1 Cycle per Hour 1 Cycle per Day X X X X X X X X X X X X X X X X X X X X X Frequency Timebase XTAL Line
All bits in the clock control register are reset by a power-on reset. Therefore, XTAL is selected as the clock output at this time. INTERRUPT CONTROL REGISTER (READ/WRITE) -- READ ADDRESS $32/WRITE ADDRESS $B2
MSB D7 D6 D5 D4 ALARM D3 D2 D1 LSB D0
WATCH- POWER- POWER DOWN SENSE DOG
PERIODIC SELECT
B C D
All bits are reset low by power-on reset.
Watchdog When this bit is set high, the watchdog operation is enabled. This function requires the CPU to toggle the SS pin periodically without a serial transfer requirement. In the event this does not occur, a CPU reset is issued at the CPUR pin. The status register must be read before re-enabling the watchdog function. Power-Down A high in this location initiates a power-down. A CPU reset occurs via the CPUR output, the CLKOUT and PSE output pins are reset low, and the serial interface is disabled. Power Sense When set high, this bit is used to enable the LINE input pin to sense a power failure. When power sense is selected, the input to the 50/60 Hz prescaler is disconnected; therefore, crystal operation is required. An interrupt is generated when a power failure is sensed and the power sense and interrupt true bit in the status register are set. When power sense is activated, a logic low must be written to this location followed by a high to re-enable power sense.
E F
STATUS REGISTER (READ ONLY) -- ADDRESS $30
MSB D7 0 D6 WATCH- DOG D5 0 D4 FIRST TIME- UP D3 INTERRUPT TRUE D2 POWER SENSE INT D1 ALARM INT LSB D0 CLOCK INT
NOTE All bits are reset low by a power-on reset except the first time-up bit which is set high. All bits except the power sense bit are reset after a read of the status register. Watchdog If this bit is set high, the watchdog circuit has detected a CPU failure. First Time-Up Power-on reset sets this bit high. This signifies the data in the RAM and Clock is not valid and should be initialized.
MOTOROLA
MC68HC68T1 15
After the status register is read, the first time-up bit is set low if the POR pin is high. Conversely, if the POR pin is held low, the first time-up bit remains set high. Interrupt True A high in this bit signifies that one of the three interrupts (power sense, alarm, or clock) is valid. Power-Sense Interrupt This bit set high signifies that the power-sense circuit has generated an interrupt. This bit is not reset after a read of this register. Alarm Interrupt When the contents of the seconds, minutes, and hours time counters and alarm latches are equal, this bit is set high. The status register must be read before loading the interrupt control register for valid alarm indication after the alarm activates. Clock Interrupt A periodic interrupt sets this bit high (see Table 3).
becomes active. Therefore, either SCK polarity is accommodated. Input data (MOSI) is latched internally on the internal strobe edge and output data (MISO) is shifted out on the shift edge (see Table 4 and Figure 13). There is one clock for each bit transferred. Address as well as data bits are transferred in groups of eight. Table 4. Function Table
Signal Mode Disabled Reset Write SS L H SCK Input Disabled CPOL = 1 CPOL = 0 Read H CPOL = 1 CPOL = 0 X Next Data Bit Shifted Out* MOSI Input Disabled Data Bit Latch MISO High-Z High-Z
* MISO remains at a High-Z until eight bits of data are ready to be shifted out during a read. MISO remains at a High-Z during the entire write cycle.
ADDRESS AND DATA FORMAT There are three types of serial transfers: 1. Read or write address 2. Read or write data 3. Watchdog reset (actually a non-transfer) The address and data bytes are shifted MSB first, into the serial data input (MOSI) and out of the serial data output (MISO). Any transfer of data requires the address of the byte to specify a write or read Clock or RAM location, followed by one or more bytes of data. Data is transferred out of MISO for a read operation and into MOSI for a write operation (see Figures 14 and 15).
SERIAL PERIPHERAL INTERFACE (SPI)
The serial peripheral interface (SPI) utilized by the MC68HC68T1 is a serial synchronous bus for address and data transfers. The shift clock (SCK), which is generated by the microcomputer, is active only during address and data transfer. In systems using the MC68HC05C4 or MC68HC11A8, the inactive clock polarity is determined by the clock polarity (CPOL) bit in the microcomputer's control register. A unique feature of the MC68HC68T1 is that the level of the inactive clock is determined by sampling SCK when SS
MC68HC68T1 16
MOTOROLA
SS CPOL = 1* SCK
SHIFT
INTERNAL STROBE
SS
SHIFT
INTERNAL STROBE
CPOL = 0* SCK
MOSI * CPOL is a bit that is set in the microcomputer's Control Register.
MSB
MSB-1
Figure 13. Serial Clock (SCK) as a Function of MCU Clock Polarity (CPOL)
SS
SCK*
MOSI
A7 MSB
A6
A5
A4
A3
A2
A1
A0 LSB
* SCK can be either polarity.
Figure 14. Address Byte Transfer Waveforms
SS
SCK*
MSB D7 D6 D5 D4 D3 D2 D1
LSB D0
MOSI
MSB D7 D6 D5 D4 D3 D2 D1
LSB D0
MISO
* SCK can be either polarity.
Figure 15. Read/Write Data Transfer Waveforms
MOTOROLA
III III III III III
MC68HC68T1 17
IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII
IIIIII IIIIII IIIIII IIIIII IIIIII II II II II II II II II
Address Byte The address byte is always the first byte entered after SS goes true. To transmit a new address, SS must first be brought low and then taken high again.
MSB A7 A6 A5 A4 A3 A2 A1 LSB A0
Address and Data Data transfers can occur one byte at a time or in multi-byte burst mode (see Figures 16 and 17). After the MC68HC68T1 is enabled (SS = high), an address byte selects either a read or a write of the Clock/Calendar or RAM. For a single-byte read or write, one byte is transferred to or from the Clock/Calendar register or RAM location specified by an address. Additional reading or writing requires re-enabling the device and providing a new address byte. If the MC68HC68T1 is not disabled, additional bytes can be read or written in a burst mode. Each read or write cycle causes the Clock/Calendar register or RAM address to automatically increment. Incrementing continues after each byte transfer until the device is disabled. After incrementing to $1F or $9F, the address wraps to $00 and continues if the RAM is selected. When the Clock/Calendar is selected, the address wraps to $20 after incrementing to $32 to $B2.
A7 -- High initiates one or more write cycles. Low initiates one or more read cycles. A6 -- Must be low (zero) for normal operation. A5 -- High signifies a clock/calendar location. Low signifies a RAM location. A0 - A4 -- Remaining address bits (see Figure 5).
SS
SCK
WRITE
MOSI
ADDRESS BYTE
MOSI READ
ADDRESS BYTE
MISO
Figure 16. Single-Byte Transfer Waveforms
SS
WRITE
MOSI
ADDRESS BYTE
MOSI READ
ADDRESS BYTE
MISO
W/R ADDRESS
ADDRESS BYTE ADDRESS BYTE + 1 ADDRESS BYTE + n
Figure 17. Multiple-Byte Transfer Waveforms
MC68HC68T1 18
IIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIII IIII III I IIIIIIIIIIIIIIIIII IIII IIII
IIII IIII IIII IIII IIII IIII IIII IIII
SCK
IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII
DATA BYTE DATA BYTE DATA BYTE 0 DATA BYTE 1 DATA BYTE n DATA BYTE 0 DATA BYTE 1 DATA BYTE n
IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII
MOTOROLA
APPLICATION CIRCUITS
LOW VOLTAGE AC LINE
BRIDGE/ REGULATOR 100 k NOTE 2 16 VDD 10 POR INT 3 11 NOTE 1 LINE VSYS 12 VDD MC68HC68T1 13 VBATT 2 NOTE 3 7 4 5 6 34 33 32 31 1 MC68HC05C4 38 0.1 mF 2 40 VDD 39
IRQ
CPUR
RESET
SS SCK MOSI MISO XTALin 14
PORT SCK MOSI MISO
NOTES: 1. Clock circuit driven by line input frequency. 2. Power-on reset circuit included to detect power failure. 3. If an MC68HC11 MCU is used, delete the capacitor at the RESET pin.
Figure 18. Power-Always-On System
MOTOROLA
MC68HC68T1 19
AC LINE
BRIDGE/ REGULATOR RCHARGE 100 k 13 VBATT 14 VSYS NOTE 2 15 MC68HC68T1 11 NOTE 1 LINE CPUR 2 NOTE 3 CLKOUT SS MISO MOSI SCK 1 7 6 5 4 39 28 31 32 33 OSC 1 PORT (e.g., PC0) MISO MOSI SCK 1 INT 3 VDD 2 IRQ MC68HC05C4 RESET 12 10 16 VDD POR 0.1 mF 40 VDD
NOTES: 1. The LINE input pin can sense when the switch opens by use of the power sense interrupt. The MC68HC68T1 crystal drives the clock input to the CPU using the CLKOUT pin. On power-down when V SYS < V BATT + 0.7 V, V BATT powers the clock. A threshold detect activates an on-chip P channel switch, connecting V BATT to V DD. V BATT always supplies power to the oscillator, keeping voltage frequency variation to a minimum. 2. For 32.768 kHz oscillator, see Figure 12. This configuration, when the MC68HC68T1 supplies the MCU clock, usually requires a 1 to 4 MHz clock. 3. If an MC68HC11 MCU is used, delete the capacitor at the RESET pin.
Figure 19. Externally-Controlled Power System
POWER-SENSING POWER-DOWN PROCEDURE
A procedure for power-down operation consists of the following: 1. Set power sense operation by writing bit 5 high in the interrupt control register. 2. When an interrupt occurs, the CPU reads the status register to determine the interrupt source. 3. Sensing a power failure, the CPU does the necessary housekeeping to prepare for shutdown.
4. The CPU reads the status register again after several milliseconds to determine validity of power failure. 5. The CPU sets power-down (bit 6) and disables all interrupts in the interrupt control register when power-down is verified. This causes the CPU reset and Clock Out pins to be held low and disconnects the serial interface. 6. When power returns and VSYS rises above VBATT + 0.7 V, power-up is initiated. The CPU reset is released and serial communication is established.
MC68HC68T1 20
MOTOROLA
AC LINE
BRIDGE/ REGULATOR NC
(EPS) ENABLED POWER SUPPLY
100 k RCHARGE 0.1 mF 13 10 POR VBATT 16 VDD 12 VSYS 40 VDD
NOTE 1
PSE 14 MC68HC68T1 XTAL 15 CPUR
9 MC68HC05C4 2 VDD NOTE 2 1 RESET
11
LINE VSS 8
INT CLKOUT SS SPI
3 1 7 3
2 39 28
IRQ OSC 1 PORT SPI VSS 20
NOTES: 1. See Figure 12 for 32.768 kHz operation. This configuration, where the MC68HC68T1 supplies the MCU clock, usually requires a 1 to 4 MHz crystal. 2. If an MC68HC11 MCU is used, delete the capacitor at the RESET pin.
Figure 20. Rechargeable Battery-Backup System
MOTOROLA
MC68HC68T1 21
CLOCK BUTTON
IGNITION
ENABLED POWER
5V REG + 12 V - 100 kW 13 0.1 mF 10 VBATT POR 11 LINE 16 12 VDD VSYS 40 VDD PORT
28
PSE
9 MC68HC05C4 2 NOTE 2 1 39 2 7 3 27 1 RESET
NOTE 1
MC68HC68T1 14 XTAL CPUR 2 MHz
15
CLKOUT INT SPI VSS 8 SS
3
OSC 1 IRQ SPI PORT 20 VSS
NOTES: 1. The VSYS and Line inputs can be used to sense the ignition turning on and off. An external switch is included to activate the system without turning on the ignition. Also, the CMOS CPU is not powered down with the system VDD, but is held in a low power reset mode during power-down. When restoring power, the MC68HC68T1 enables the CLKOUT pin and sets the PSE and CPUR pins high. 2. If an MC68HC11 MCU is used, delete the capacitor at the RESET pin. 3. Voltage at pin must not exceed absolute maximum Vin specification.
Figure 21. Automotive System
MC68HC68T1 22
MOTOROLA
3.0 V NON-RECHARGEABLE BATTERY 1 kW - + RLIMIT 0.1 mF 0.1 mF 11 6 5 3 7 4 13 VBATT LINE MISO MOSI INT SS SCK POR XTALout 16 12 VDD VSYS 10 15 DBLOCK
VCC
100 kW 0.1 mF
215 kW* 10 MW 32.768 kHz 10 pF* 39 pF*
XTALin MC68HC68T1 CLKOUT
14
1 9
2
CPUR VSS 8
PSE
* Actual values may vary, depending on recommendations of crystal manufacturer.
Figure 22. Non-Rechargeable Battery-Backup System
MOTOROLA
MC68HC68T1 23
TROUBLESHOOTING
1. The circuit works, but the standby current is well above the spec. How can the standby current be reduced? a. If using a 32.768 kHz crystal, include a series resistor in the circuit per Figure 12 of the data sheet. A good value to start with is 200 kW. The signals at XTALout and XTALin pins should look similar to Figure 23 when the correct value is selected. The sharp, clean edges on the XTALout pin reduces current on the totem pole drivers internal to the device.
APPROXIMATELY 30.52 ms SEE NOTE
4. When the part is power cycled, the clock loses all time and data. Check the battery installation and ensure that a diode is in the circuit from VDD to + 5 V. 5. Can a non-rechargeable lithium battery be used? Yes, but the battery must have a large capacity. Careful attention MUST be given if the end unit needs to be UL approved. The circuit of Figure 22 is a good start. 6. Able to read/write data to the RAM but not to the clock registers, or vice versa. There is a software problem. There is no internal difference from reading/writing to the RAM or clock locations. 7. How is the oscillator tuned? The best way to tune the oscillator is to set the clock out bits of the Clock Control Register (bits 0, 1, and 2) to output the primary XTAL frequency (000). The frequency can then be more accurately measured from the CLKOUT pin. This prevents the measuring device from loading the oscillator circuit, which may shift the frequency. 8. What is the accuracy of the oscillator? The oscillator accuracy is dependent on the quality of the crystal used. For every 1 ppm variance in crystal frequency, the clock gains or loses 2.6 seconds per month. 25 ppm is a typical spec for a crystal, which translates to 65 seconds per month.
VBATT
0V XTALout
1 TO 2 V p-p XTALin NOTE: Refer to item 8.
"
9. Can the Line pin sense a dc failure? Yes, the Line input is threshold triggered in a window from one diode drop above and below V DD . If supply is removed in the low cycle of a sine wave, the internal network pulls the line pin to within the threshold in a few milliseconds. In the absence of a dc voltage outside the VDD 0.7 V window, the internal network pulls the signal to within the window and triggers the interrupt. 10. Can the VSYS line be more than 0.5 V above VDD ? No. There is an ESD protection network that causes a supply problem with this application. 11. The CLKOUT, CPUR, and PSE pins do not go inactive when VDD and VSYS are removed. The CLKOUT, CPUR, and PSE are not active immediately when VDD and VSYS is applied. The problem is related to the power up procedure (battery-backup mode or single-supply mode). See these sections in the data sheet for more information.
Figure 23. XTAL Waveforms b. Connect the LINE pin to something other than VDD (e.g., VBATT, VSS, VSYS) c. Ensure that the Power-On-Reset (POR) has a time constant of at least 100 ms. d. Ensure that there is a diode from VDD to + 5 V of the system, in battery-backup applications. See Application Circuits. 2. When power is applied, the clock does not start up nor does it hold data in the control registers. Make sure the POR circuit is connected and working. 3. The clock loses time, but the oscillator is tuned. Do not make constant accesses to the clock. When a read or write cycle is started, the clock stops incrementing time.
MC68HC68T1 24
MOTOROLA
PACKAGE DIMENSIONS
P SUFFIX PLASTIC DIP (DUAL IN-LINE PACKAGE) CASE 648-08
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION "L" TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION "B" DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. 6. 648-01 THRU -07 OBSOLETE, NEW STANDARD 648-08. DIM A B C D F G H J K L M S MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01 INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.070 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040
-A16 9
B
1 8
F S
C -TK
SEATING PLANE
L
H G D 16 PL 0.25 (0.010) M
J
M
T
A
M
DW SUFFIX SOG (SMALL OUTLINE GULL-WING) PACKAGE CASE 751G-01 -A16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0 7 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0 7 0.395 0.415 0.010 0.029
-B1 8
P
8 PL
0.25 (0.010)
M
B
M
G R X 45 -TD 16 PL 0.25 (0.010)
M
C K TB
S
SEATING PLANE
M
F
J
A
S
DIM A B C D F G J K M P R
MOTOROLA
MC68HC68T1 25
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com
JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MC68HC68T1 26
*MC68HC68T1/D*
MC68HC68T1/D MOTOROLA

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